R. Bazylevych , V. Andrienko
The graphs bisectioning algorithms are investigated and their applicability to islanding of the power system. The Kernighan-Lin algorithm, spectral method and multilevel kernel k - means approach have been analyzed with respect to the computational complexity and their applicability.

1.Острівкування. 2. Peiravi A., R. Ildarabadi. "Comparison of Computational Requirements for Spectral and Kernel k-means Bisectioning of Power Systems", Australian Journal of Basic and Applied Sciences, 3(3): 2366-2388, 2009. 3. Agematsu, S., S. Imai, R. Tsukui, H. Watanabe, T. Nakamura, T. Matsushima. “Islanding Protection System with Active and Reactive Power Balancing Control for Tokyo Metropolitan Power System and Actual Operational Experiences,” in Proceedings of the 7th IEE Int. Conf. Developments in Power System Protection, pp: 351–354. , 2001. 4.Cherng, J., S. Chen, C. Tsai, J. Ho, 1999. An efficient two-level partitioning algorithm for VLSI circuits, Proceedings of the 1999 Design Automation Conference, ASP-DAC '99, Asia and Pacific, 1: 69-72, Wanchai, Hong Kong, 18-21 Jan. 1999. 5.Cherng, J., S. Chen, 2003. An efficient multi-level partitioning algorithm for VLSI circuits, Proceedings of the 16th 70-75. International Conference on V LSI Design (VLSI'03), 4-8 January 2003. 6.Dhillon, Inderjit S., Guan, Yuqiang, Kulis, Brian, 2005. “A Fast Kernel Based Multilevel Algorithm for Graph Partitioning,” In the Proceedings of the 11th ACM SIGKDD International Conference on Knowledge Discovery Data Mining (KDD), pp: 629-634. 7. Hagen, L., A.B. Kahng, 1992. “New Spectral Methods for Ratio Cut Partitioning and Clustering,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 11(9): 1074-1085. 8.Holzrichter, M ., S. Oliveira, 1999. A graph based method for generating the Fiedler vector of irregular problems, Proceedings of the 11 IPPS/SPDP'99 Workshops Held in Conjunction with the 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing, San Juan, P.R., pp: 978-985. 9. Karypis, G., V. Kumar, 1999. "A Fast and High Quality Multilevel Scheme for Partitioning Irregular Graphs", SIAM J. Scientific Computing, 20(1): 359-392. 10. SC99. 11. Kernighan, B.W., S. Lin, 1970. “An efficient heuristic procedure for partitioning graphs,” The Bell System Technical Journal, 49(2). Peiravi, A., R. Ildarabadi, 2009. A fast algorithm for intentional islanding of power systems using the multilevel kernel k-means approach, Journal of Applied Sciences, 9(12): 2247-2255. 12. Rajamani, K., U.K. Hambarde, 1999. “Islanding and Load Shedding Schemes for Captive Power Plants,” IEEE Trans. on Power Del., 14(3): 805–809.13. Rehtanz, C., 2003. Autonomous systems and intelligent agents in power system control and operation, Springer. 14. Venkatasubramanian, V., J. Quintero, 2005. “Detection, Prevention and Mitigation of Cascading Events-Part II”, Power System Engineering Research Center, A National Science Foundation Industry/University Cooperative Research Center Since 1996, PSERC Publication 05-60.15.Vittal, V., Xiaoming Wang, 2005. “Detection, Prevention and Mitigation of Cascading Events-Part III”, Power System Engineering Research Center, A National Science Foundation Industry/University Cooperative Research Center Since 1996, PSERC Publication 05-61, October 2005.16.Wang, X.Z., Z. Yan, W. Xue, 2008. “An adaptive clustering algorithm with high performance computing application to power system transient stability simulation”, 3rd International Conference on Deregulation and Restructuring and Power Technologies, DRPT 2008, art. no. 4523578, pp: 1137-1140.17.Wang, X., Vittal, V., 2004. “System Islanding using Minimal Cutsets with Minimum Net Flow”, In Proceedings of the IEEE Power Eng. Soc. Power Syst. Conf. Expo., New York, 1: 379-384.18.Mohar, B., 1991. “The Laplacian Spectrum of Graphics,” in Graph Theory, Combinatorics, and Applications, Vol. 2, Ed. Y. Alavi, G. Chartrand, O . R. O ellermann, A. J. Schwenk, W iley, New York, pp: 871-898. 19.Базилевич Р.П. “Декомпозиционные и топологические методы автоматиированного проектирования электронных устройств”, Львов, «Вища школа», 1981, 168 С.20.R.P. Bazylevych, R.A. Melnyk, O.G. Rybak. “Circuit partitioning for FPGAs by the optimal circuit reduction method”. In: VLSI Design, Vol. 11, No 3, pp. 237-248, 2000.21.Bazylevych R.P. “The optimal circuit reduction method as an effective tool to solve large and very large size intractable combinatorial VLSI physical design problems”. In: 10-th NASA Symp. on VLSI Design, March 20-21, 2002, Albuquerque, NM, USA, pp. 6.1.1-6.1.14. 22.R. Bazylevych, I. Podolskyy and L.Bazylevych. “Partitioning optimization by recursive moves of hierarchically built clusters”. In: Proc. of 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. April, 2007, Krakow, Poland, pp. 235-238.23.Roman Bazylevych, Marek Pałasiński, Dmytro Yanush, Lubov Bazylevych. “Partitioning Optimization by Iterative Reassignment of the Hierarchically Built Clusters with Border Elements”, 2nd Mediterranean Conference on Embedded Computing, MECO – 2013, Budva, Montenegro, pp.219-222.